RiscEmu: Instructions

Index

• Register Instructions (new)
• Load/Store Instructions
• Control Instructions
• Special Instructions
• Notes

Register Instructions (index)

• ADD a b c
R.a = R.b + R.c
  
  
• SUB a b c
R.a = R.b - R.c
  
  
• MUL a b c
R.a = R.b * R.c
  
  
• DIV a b c
R.a = R.b DIV R.c
  
  
• MOD a b c
R.a = R.b MOD R.c
  
  
• CMP a b c
R.a = R.b - R.c
  When the difference is outside the range -2³¹ <= x-y < 2³¹, CMP yeilds a result with the wrong magnitude but with the correct sign
  
  
• OR a b c
R.a = R.b OR R.c
  
  
• AND a b c
R.a = R.b & R.c
  
  
• BIC a b c
R.a = R.b & ~ R.c
  
  
• XOR a b c
R.a = R.b XOR R.c
  
  
• LSH a b c
R.a = LSH(R.b R.c)
  
  
• ASH a b c
R.a = ASH(R.b R.c)
  
  
• CHK a c
0 <= R.a < R.c
  
  
• ADDI a b c
R.a = R.b + c
  
  
• SUBI a b c
R.a = R.b - c
  
  
• MULI a b c
R.a = R.b * c
  
  
• DIVI a b c
R.a = R.b DIV c
  
  
• MODI a b c
R.a = R.b MOD c
  
  
• CMPI a b c
R.a = R.b - c
  When the difference is outside the range -2³¹ <= x-y < 2³¹, CMP yelds a result with the wrong magnitude but with the correct sign
  
  
• ORI a b c
R.a = R.b OR c
  
  
• ANDI a b c
R.a = R.b & c
  
  
• BICI a b c
R.a = R.b & ~ c
  
  
• XORI a b c
R.a = R.b XORI c
  
  
• LSHI a b c
R.a = LSH(R.b c)
  
  
• ASHI a b c
R.a = ASH(R.b c)
  
  
• CHKI a c
0 <= R.a < c
  
  
• ADDIU a b c
R.a = R.b + c (unsigned)
  
  
• SUBIU a b c
R.a = R.b - c (unsigned)
  
  
• MULIU a b c
R.a = R.b * c (unsigned)
  
  
• DIVIU a b c
R.a = R.b DIV c (unsigned)
  
  
• MODIU a b c
R.a = R.b MOD c (unsigned)
  
  
• CMPIU a b c
R.a = R.b - c (unsigned)
  
  
• ORIU a b c
R.a = R.b OR c (unsigned)
  
  
• ANDIU a b c
R.a = R.b & c (unsigned)
  
  
• BICIU a b c
R.a = R.b & ~ c (unsigned)
  
  
• XORIU a b c
R.a = R.b XORI c (unsigned)
  
  
• CHKIU a c
0 <= R.a < c (unsigned)
  
  

Load/Store Instructions (index)

• LDW a b c
R.a = Mem[R.b + c]
  load word
  
  
• LDB a b c
R.a = Mem[R.b + c]
  load byte
  
  
• POP a b c
R.a = Mem[R.b];
R.b = R.b + c
  pop stack
  
  
• STW a b c
Mem[R.b + c] = R.a
  store word
  
  
• STB a b c
Mem[R.b + c] = R.a
  store byte
  
  
• PSH a b c
R.b = R.b - c;
Mem[R.b] = R.a
  push stack
  
  

Control Instructions (index)

The target addresses of branch instructions are word addresses.

• BEQ a c
  Branch to c if R.a = 0
  
  
• BNE a c
  Branch to c if R.a # 0
  
  
• BLT a c
  Branch to c if R.a "<" 0
  
  
• BGE a c
  Branch to c if R.a >= 0
  
  
• BLE a c
  Branch to c if R.a <= 0
  
  
• BGT a c
  Branch to c if R.a > 0
  
  
• BSR c
  Save PC in R31, then branch to c (address PC relative)
  
  
• JSR c
  Save PC in R31, then jump to c (address absolute)
  
  
• RET c
  Jump to address in R.c (address absolute)
  
  

Special Instructions (index)

• RD a
R.a = input
  
  
• WRD c
prints R.c
  
  
• WRH c
prints R.c
  
  
• WRL
prints a newline
  
  

Notes (index)

• The immediate field c is 16 bit wide
  unsigned: -2¹⁵ <= c < 2¹⁵
  signed: 0 <= c < 2¹⁶